1. Field of the Invention
This invention relates generally to semiconductor memory devices and memory access systems, and more particularly, to a semiconductor memory device and a memory access system using an address signal having four states for high speed operation. The invention has particular applicability to dynamic random access memories (DRAMs).
2. Description of the Background Art
Recently, semiconductor memories have been widely used in various electronic apparatus. In particular, a dynamic random access memory (hereinafter referred to as a "DRAM") has a larger storage capacity compared to other semiconductor memories, for example a static random access memory (hereinafter referred to as an "SRAM"), and therefore it is frequently employed for data storage in a computer system. That is, a DRAM is used to constitute for example a main memory in a computer system because of its low cost per bit in data storage and high degree of integration.
With the advancement of recent VLSI design and process technology, an operation speed of a microprocessor has become higher, and higher speed memory access has become necessary in a computer system. That is, a semiconductor memory used in a computer system, for example, a DRAM, a SRAM, etc. needs to operate at a higher speed. Under this situation, the operation speed of a DRAM and a SRAM has become higher in recent years, and it is predicted that the operation speed will reach almost the limit in the near future. The invention is applicable generally to semiconductor memories for higher speed memory access, but application to a DRAM will be described by way of an example.
FIG. 14 is a block diagram of a memory access circuit showing a background of the invention in a computer system. Referring to FIG. 14, this memory access circuit comprises a microprocessing unit (hereinafter referred to as an "MPU") 1 and a DRAM 110 accessed by MPU 1. The following circuit is provided for the interface between MPU 1 and DRAM 110. In the following description, it is assumed that DRAM 110 has a memory capacity of 16M bits.
An address expansion circuit 2 performs a process for expanding address space in order to handle memory space exceeding address space which allows direct addressing by MPU 1. A real address converter 3 receives a virtual address signal VA generated from MPU 1 and generates row address signals RA0 through RA11 and column address signals CA0 through CA11 for access to DRAM 110 by real address conversion. An address multiplexer 105 receives row address signals RA0 through RA11 and column address signals CA0 through CA11, and performs switching operation for address multiplexing. That is, address multiplexer 105 outputs row address signals RA0 through RA11 and column address signals CA0 through CA11 alternately, that is, in a time division multiplexing manner, in response to a switching control signal /MPX generated from a timing controller 106. Consequently, a row address signals and a column address signals which have 24 bits in total can be obtained as 12 bit address signals A0-A11 by performing a time division multiplexing process. Address signals A0 through A11 are applied to DRAM 110 through an address buffer 107. MPU 1 can access not only DRAM 110 but also other memory devices and input/output devices, etc. (not shown).
In the memory access circuit shown in FIG. 14, only control signals to access DRAM 110 are indicated. When MPU 1 requires a read operation to DRAM 110, MPU 1 applies a memory read signal /MR to timing controller 106. When MPU 1 requires a write operation to DRAM 110, MPU 1 applies a memory write signal /MW to timing controller 106. In addition, MPU 1 applies state signals /S0 and /S1 to timing controller 106 to show a status of an operation cycle in MPU. Timing controller 106 applies a wait signal /WAIT to MPU 1 in a period of memory access to DRAM 110. Timing controller 106 generates a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE and a switching control signal /MPX. Signals /RAS, /CAS and /WE are applied to DRAM 110 through a control signal driver 8. A data buffer 9 is connected between MPU 1 and DRAM 110, and data buffer 9 transfers data D to/from DRAM 110 in response to a write control signal /WR generated from timing controller 106.
FIGS. 15(a) to 15(k) are time charts of a read cycle in the memory access circuit shown in FIG. 14. In the following description, it is assumed that a read cycle and a write cycle are performed in 4 period of a reference clock signal CLK. Referring to FIGS. 15(a) to 15(k), a memory access request signal /CS and state signals /S0 and /S1 generated by decoding memory address signals are sampled in response to the fall of a clock signal CLK. A signal /RAS and a signal /MPX fall in response to the first fall of a clock signal CLK. Address multiplexer 105 first outputs row address signals RA0 through RA11, and in response to the fall of a signal /MPX it is switched and outputs column address signals CA0 through CA11. In a timing chart of FIGS. 15(a) to 15(k) only i-th bit is indicated among address signals A0 through A11 of 12 bits in total. Therefore, in response to a signal /MPX, i-th row address signal RAi is switched to i-th column address signal CAi. Thus, address signals A0 through A11 of 12 bits each processed in a time division multiplexing manner are generated from address multiplexer 105. A signal /CAS falls in response to the second rise of clock signal CLK (period T2). Address signals A0 through A11 processed in a time division multiplexing manner are applied to DRAM 110 through address buffer 107 and then a read operation from DRAM 110 is performed.
FIGS. 16(a) to 16(k) are time charts of a write cycle in the memory access circuit shown in FIG. 14. The write cycle is also performed in four periods of clock signal CLK. Referring to FIGS. 16(a) to 16(k), in response to the first rise of clock signal CLK, signals /RAS and /MPX rise. Therefore, in response to signal /MPX, address multiplexer 105 outputs column address signals CA0 through CA11 in stead of row address signals RA0 through RA11. Address signals processed in a time division multiplexing manner are applied to DRAM 110 through address buffer 107 as address signals A0 through A11 of 12 bits, and then a read operation from DRAM 110 is performed.
As an operation speed of microprocessor, that is, MPU has recently been increased, there is an increasing requirement for a DRAM having a higher operation speed. An operation speed of a DRAM has been increased as the generation of a DRAM advances. In a DRAM having memory capacity of 4 megabits or 16 megabits, 60 ns or 120 ns cycle time has already been achieved. It is predicted that this trend is going to continue in future and that the access time will be more shortened. In addition, it is also predicted that the time length allowed for access control between a MPU and a DRAM will be shorter and access control timing will be more complicated.
FIG. 17 is a block diagram of the conventional DRAM 110 shown in FIG. 14. Referring to FIG. 17, the DRAM 110 comprises a memory cell array 11 including a number of memory cells arranged in columns and rows, a row decoder 12 for selecting a memory cell row, a column decoder 13 for selecting a memory cell column, a sense amplifier 14 for amplifying a data signal read from a memory cell. One address buffer 115 receives address signals A0 through A11 processed in a time division multiplexing manner by the aforementioned address multiplexer 105. A clock signal generator 118 generates various clock signals necessary for the operation of DRAM 110 in response to signals /RAS, /CAS and /WE. A data input buffer 16 receives a data signal Din to be written and applies it to memory cell array 11 through an IO bus. A data output buffer 17 receives and outputs a read data signal Dout through an IO bus.
Address signals A0 through A11 applied to address buffer 115 include row address signals RA0 through RA11 and column address signals CA0 through CA11 processed in a time division multiplexing manner as mentioned above, and row address signals RA0 through RA11 are applied to row decoder 12 and column address signals CA0 through CA11 are applied to column decoder 13 by clock signals generated from clock signal generator 118.
FIGS. 18(a) to 18(e) are time charts for describing a read operation of a DRAM shown in FIG. 17. Referring to FIG. 18, a read operation is defined by a fall of a signal /CAS after at least time period t.sub.RCS has passed from a rise of a signal /WE. An address signal Ai processed in a time multiplexing manner is latched within address buffer 115 in response to the fall of a signal /RAS and a row address signal RAi is obtained. In addition, address signal Ai is latched within address buffer 115 in response to the fall of a signal /CAS and a column address signal CAi is obtained. Row address signal RAi and column address signal CAi latched within address buffer 115 are applied to row decoder 12 and column decoder 13, respectively. Row decoder 12 activates one word line (not shown) in response to row address signals RA0 through RA11. Sense amplifier 14 amplifies a data signal read from a memory cell connected to the activated word line. Column decoder 13 selects one bit line pair in response to column address signals CA0 through CA11, and the amplified data signal Dout is output through data output buffer 17. In FIGS. 18(a) to 18(e), /RAS access time t.sub.RAC, /CAS access time t.sub.CAC and address access time t.sub.AA are indicated. An output terminal Dout is normally brought into high impedance state (Hi-Z), but it is activated only when the read data signal is output. In FIGS. 18(a) to 18(e), /RAS active time t.sub.RAS and /RAS precharge time t.sub.RP are also indicated.
FIGS. 19(a) to 19(e) are time charts for describing the write operation of the DRAM shown in FIG. 17. The time chart shows an early write operation. That is, a write operation is started by the fall of a signal /WE prior to the fall of a signal /CAS. Similarly to the read operation shown in FIGS. 18(a) to 18(e), a row address signal RAi and a column address signal CAi processed in a time multiplexing manner are latched within address buffer 115, and a data signal Din applied through a data input buffer 16 is written to the memory cell designated by these address signals.
FIG. 20 is a circuit diagram of memory cell array 11 and peripheral circuit thereof shown in FIG. 17. Referring to FIG. 20, a memory cell M comprises an NMOS transistor Qs for switching and capacitor Cs for storing a data signal. The memory cell M is connected to a j-th bit line BLj. Transistor Qs has its gate connected to a k-th word line WLk. Sense amplifier 14 comprises NMOS transistors Q1 and Q2, and PMOS transistors Q3 and Q4. The sense amplifier 14 is activated in response to sense amplifier activation signals .phi..sub.N and .phi..sub.P.
FIGS. 21(a) to 21(h) are time charts for describing the operation of the circuit shown in FIG. 20. Referring to FIGS. 20 and 21, a read operation will be described below. The potential of word line WLk is raised by a row decoder, so that transistor Qs is turned on. Therefore, a very small potential difference appears between bit line pair BLj and /BLj. Sense amplifier 14 is activated in response to an activation of sense amplifier activation signals Sn and Sp, so that a very small potential difference is amplified. This amplification is performed by charging and discharging a bit line pair BLj and /BLj by sense amplifier 14. Subsequently, column decoder 13 raises a signal Yj, so that gate transistors Q8 and Q9 are turned on and an amplified signal is applied to an IO bus line pair. A data signal on the IO bus line pair is output through data output buffer 17.
FIG. 22 is a block diagram of address buffer 115 shown in FIG. 17. In this figure only the circuit which handles an i-th bit Ai among address signals A0 through A11 of 12 bits. Referring to FIG. 22, the address buffer 115 comprises a row address input circuit 601 for receiving a row address signal, a switching circuit 602 for interlock, a row address latch circuit 603, a column address input circuit 604 for receiving a column address signal, a switching circuit 605 for interlock, and a column address latch circuit 606.
FIGS. 23(a) to 23(g) are timing charts for describing the operation of address buffer 115 shown in FIG. 22. Referring to FIGS. 22 and 23, the operation will be described. Control signals /RASA, /RAI, /RAL, /CASA, /CAI and /CAL are generated from clock signal generator 18 shown in FIG. 17.
A signal /RASA falls at time t1, so that a row address signal RAi which is the first half of an applied address signal Ai is received by a row address input circuit 601. Subsequently, at time t2, signal /RAI falls, so that the received signal is applied to a row address latch circuit 603 through a switching circuit 602. At time t3 a signal /RAL falls, so that row address latch circuit 603 latches applied row address signal RAi. At time t4, a column address signal CAi which is the latter half of an address signal Ai is applied. At time t5 a signal /CASA falls, so that a column address signal CAi is received by a column address input circuit 604. At time t6 a signal /CAI falls, so that the received column address signal CAi is applied to a column address latch circuit 606 through a switching circuit 605. At time t7, a signal /CAI falls, so that column address latch circuit 606 latches column address signal CAi. Row address signal RAi and column address signal CAi latched within latch circuit 603 and 606 respectively are transferred to row decoder 12 and column decoder 13, respectively.
As can be seen from FIGS. 23(a) to 23(g), in the period from time t3 when signal /RAL falls to time t4, row address signal RAi must be latched within a row address latch circuit 603. However, the time length of this period .DELTA.t becomes shorter and shorter, as an operation speed of the DRAM increases. As the time length .DELTA.t becomes shorter, row address signal RAi needs to be certainly latched in this short time length .DELTA.t. Otherwise, a correct address signal is not supplied to row decoder 12 and therefore incorrect access is caused.
Such a problem is considered to result from adopting an address multiplexing system in a DRAM. That is to say, timing control in the switch is difficult because row address signals and column address signals are supplied in a time division multiplexing manner through one address terminal. A pseudo-SRAM has been developed conventionally in order to avoid such a problem. A pseudo-SRAM has a large capacity of a DRAM and usability of a SRAM. The aforementioned problem in latch timing of address signals processed in a time division multiplexing manner can be avoided, since the aforementioned address multiplexing system is not adopted. However, address input pins for receiving a row address signal and a column address signal respectively are needed, so that twice as many address input pins as those in a DRAM having the same memory capacity are required. This implies that it is necessary to enlarge the package of the pseudo-SRAM, and therefore a decline in packaging efficiency on a printed board cannot be avoided.
In addition to the above problem, the following problem is also pointed out concerning power consumption of a DRAM. FIG. 24(A) is a schematic diagram showing a memory cell size of a memory cell array 11 shown in FIG. 17. DRAM 110 shown in FIG. 17 is accessed in response to row address signals RA0 through RA11 and column address signals CA0 through CA11 each having 12 bits. Since the numbers of bits of a row address and a column address are the same, the same number of memory cells, that is, 4090 (=2.sup.12) memory cells are provided in each of a row direction and a column direction. That is to say, as shown in FIG. 24(A), 2.sup.12 memory cells MC are placed along one word line WL and 2.sup.12 memory cells MC are placed along one bit line BL. In other words, memory cell array 11 has a shape of almost square.
FIGS. 25(a) and 25(b) are waveform diagrams showing the change of a power consumption level of a conventional DRAM. Referring to FIGS. 25(a) and 25(b), consumption current Irow indicates the maximum current consumed by a row address system circuit and current Iary indicates the maximum current consumed in one read operation in memory cell array 11. Current Icul indicates the maximum current consumed by a column address system circuit and current Ires indicates the maximum current consumed for reset. As can be seem from FIGS. 25(a) and 25(b), current Iray consumed by a memory cell array and its peripheral circuit in one read operation is larger than any other consumption current, and therefore, when this consumption current Iary is supplied from a power supply potential Vcc, a power supply level falls by .DELTA.V because of a voltage drop. This voltage drop can be a cause of malfunction which may occur in this DRAM.
FIG. 26(A) is a graph showing consumption current in a conventional DRAM. Referring to FIG. 26(A) power Pary consumed by a memory cell array and its peripheral circuit occupies more than a half of all the power consumption and the rest is occupied by power consumption Pcul of column system circuit and power consumption Prow by a row system circuit. The reason why the current consumed by the memory cell array and its peripheral circuit is large is described below.
As shown in FIG. 20, a sense amplifier 14 is connected to each of bit lines of memory cell array 11. As described above, sense amplifier 14 consumes large current to charge and discharge bit lines BLj and /BLj. Therefore, power consumption of sense amplifier 14 occupies the large part of power consumption Pary shown in FIG. 26(A).
Referring again to FIG. 24(A), since 2.sup.12 memory cells MC are connected to word line WL along word line WL, 2.sup.12 sense amplifiers SA1 are connected to as many bit lines BL. 2.sup.12 sense amplifiers SA1 are activated in one read operation and each sense amplifier charge/discharge bit line BL, and therefore large power is consumed.